LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

entity piano_top is
  port(
        clk32mHz: in STD_LOGIC;
		  handtoauto: in STD_LOGIC;
		  index1: in STD_LOGIC_VECTOR(7 downto 0);
		  code1: out STD_LOGIC_VECTOR(6 DOWNTO 0);
		  high1:out STD_LOGIC;
		  spkout: out STD_LOGIC;
		  clk_out:out std_LOGIC);
end;

architecture art of piano_top is
component AUTO
  port(
        clk: in STD_LOGIC;
		  AUTO: in STD_LOGIC;
		  index2: in STD_LOGIC_VECTOR(7 downto 0);
		  index0: out STD_LOGIC_VECTOR(7 downto 0);
		  CLK2: buffer STD_LOGIC);
		  
end component;

component tone
  port(
        index: in STD_LOGIC_VECTOR(7 downto 0);
		  code : out STD_LOGIC_VECTOR(6 downto 0);
        high: out STD_LOGIC;
		  tone0: out INTEGER RANGE 0 to 47781);
end component;

component freq_divide
  port(
        clk1: in STD_LOGIC;
		  tone1: in INTEGER RANGE 0 TO 47781;
		  spks: out STD_LOGIC);
end component;

signal tone2: INTEGER RANGE 0 TO 47781;
signal indx: STD_LOGIC_VECTOR(7 downto 0);
begin
  --indx是输出
  u0:AUTO
  port map(
       clk=>clk32mHz,index2=>index1,AUTO=>handtoauto,index0=>indx,clk2=>clk_out);
		 
		 
  --index是tone中定义的输入，8位，indx主程序中定义的信号，8位	 
  --code1是piano_top顶层设计中的7位二进制码
  --tone0是tone中定义的输出，频率吧
  u1:tone    
  port map(
  index=>indx,tone0=>tone2,code=>code1,high=>high1);
  
  --
  u2:freq_divide
  port map(
  clk1=>clk32mHz,tone1=>tone2,spks=>spkout);   --spkout接喇叭
end art;





















